1. Overview

The Meissner oscillator circuit is a harmonic (sinusoidal) oscillator consisting of an active electronic element (transistor, electronic tube, etc.), an LC resonans circuit and a positive feedback.

The Meissner oscillator realized with an NPN bipolar transistor is shown on fig.1 in a common emitter circuit and on fig.2 in a common base circuit. The LC resonans circuit is connected between the power supply and the collector of the transistor. The positive feedback is realized through inductor L2, which is coupled to inductor L1 as shown on the schematics. According to the used circuit, L2 is connected to the base or to the emitter of the transistor.

2. Analysis

The resonans circuit defines the generated frequency, which can be approximately calculated using the LC resonans circuit calculator

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Open schematic in new window	Meissner Oscillator in Common Emitter Circuit

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Open schematic in new window	Meissner Oscillator in Common Base Circuit

T1, being blocked, will let C1 charge itself to the supply voltage minus the base-emitter on voltage of transistor T2 and minus the forward voltage of diode D2:

C2 will charge negatively to:

Here V_CE(sat)-T2 is the collector-emitter saturation voltage of the conducting T2, V_BE(on)-T1 is the base-emitter on voltage of T1 and V_F-D1 is the forward voltage of D1.

Once in state 1 the circuit will charge the capacitors C1 and C2 as specified. The transition to state 2 will occur when the charging of C2 completes and the base-emitter current of T1 increases. This increase will raise the voltage over R1 thus pushing the base voltage of T2 through C1 down. T2 will decrease its conductance and the voltage over R4 will raise. This will increase the base voltage of T1 and the process will result in positive feedback which will switch the circuit to conduncting T1 and non-conducting T2. During state 2 the capacitors charging will take the reverse path.

In each state of the circuit, one of the capacitors is charging through the collector resistor (R1 or R4) and the other capacitor is discharging through the base resistor (R3 or R2). The switching occurs when the capacitor charging throught the base resistor get charged. So this charging process should take longer, i.e. the base resistor should be greater than the collector resistor:

(3.) R2 > R4
(4.) R3 > R1

There is another condition for the resistors and it comes from the current amplification of each transistor, which is also called the dynamic forward current transfer ratio in common emitter circuit - h_21e. R2 and R3 should conform to:

Where 0.5 is a security factor. Finally, D1 and D2 are used to protect the base-emitter junctions of T1 and T2 from reverse voltage higher than the emitter-base maximum voltage of the used transistors. Normally, this voltage is around -5V for silicon NPN transistors. D1 and D2 are used when the power supply is higher than 5V. C3 and C4 are blocking (filtering) capacitors.

The charging effect of the capacitor through the collector resistor delivers non-rectangular output voltage from the schematic (see fig.1).

Enlarge fig.1

To obtain uniform rectangular output (fig.2) a variation of the schematic is shown below.

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Open schematic in new window	schematic 2

Enlarge fig.2

The period T of the periodic process can be approximately calculated with the following equation:

Here 0.7 * R2 * C2 is the time constant of state 1 of the circuit and 0.7 * R3 * C1 - of state 2 respectively.

The two output voltage levels V₁ and V₂ are determined as follows:

(8.) V₁ = V_CC
(9.) V₂ = V_CE(sat)-T2

Equation (8.) is valid if we assume that the leackage currents I_CEO-T2, I_L-C2 and I_R-D3are neglected. V_CE(sat)-T2 is the collector-emitter saturation voltage of T2.

3. Synthesis

The synthesis of the circuit generally starts with the selection of R1 and R4 resistors according to the needs of power load. Then the base resistors are selected using (5.) and (6.), but not to violate (3.) and (4.). After this step, the periods of state 1 and state 2 are chosen. Finally, the capacitance of C1 and C2 is calculated using (7.).