1. Overview
Radio waves Jump to: navigation, search Radio waves are electromagnetic waves occurring on the radio frequency portion of the electromagnetic spectrum. Diagram of the electric (E) and magnetic (H) fields of Radio Waves emanating from a radio transmitting antenna (small dark vertical line in the center). The E and H fields are perpendicular as implied by the phase diagram in the lower right. This is a plot of Earth's atmospheric transmittance (or opacity) to various wavelengths of electromagnetic radiation, including radio waves. Radio waves were first predicted by mathematical work done in 1865 by James Clerk Maxwell. Maxwell noticed wave-like properties of light and similarities in electrical and magnetic observations and proposed equations that described light waves and radio waves as waves of electromagnetism that travel in space. In 1887 Heinrich Hertz demonstrated the reality of Maxwell's electromagnetic waves by experimentally generating radio waves in his laboratory. Many inventions followed, making practical use of radio waves to transfer information through space. Nikola Tesla and Guglielmo Marconi are credited with inventing systems to allow radio waves to be used for communication.Radio portion of the electromagnetic spectrum Radio waves are divided into bands according to there frequency (or wavelength) as shown in the radio frequency spectrum table below. Band name Abbr ITU band Frequency and
Wavelength in air Example uses < 3 Hz > 100,000 km
Extremely low frequency ELF 1 3–30 Hz 100,000 km – 10,000 km Communication with submarines
Super low frequency SLF 2 30–300 Hz 10,000 km – 1000 km Communication with submarines
Ultra low frequency ULF 3 300–3000 Hz 1000 km – 100 km Communication within mines Very low frequency VLF 4 3–30 kHz 100 km – 10 km Submarine communication, avalanche beacons, wireless heart rate monitors, geophysics
Low frequency LF 5 30–300 kHz 10 km – 1 km Navigation, time signals, AM longwave broadcasting
Medium frequency MF 6 300–3000 kHz 1 km – 100 m AM (Medium-wave) broadcasts
This schematic has two astable states. In state 1 transistor T2 is conducting and transistor T1 is non-conducting. The feedback between the two transistors is achieved using capacitors C1 and C2. The time period for each state can be adjusted.
2. Analysis
Before starting the circuit (no voltage applied) both capacitors C1 and C2 are charged with 0V. Upon applying voltage to the circuit, even if the schematic is symmetrical, due to assymetry caused by unideal conditions, one of the transistors will conduct greater current than the other. Let's assume this is T2 that will conduct more current than T1. Thus the voltage over resistor R4 will be higher than the voltage over resistor R1. This will result to driving the base voltage of T1 to a lower value than the base voltage of T2. This T1 will become less conductive than T2. This process represents a positive feedback that will lead to immidiate switching of the schematic to state 1.
T1, being blocked, will let C1 charge itself to the supply voltage minus the base-emitter on voltage of transistor T2 and minus the forward voltage of diode D2:
(1.)| VC1 | = |
|
C2 will charge negatively to:
(2.) VC2 = VCE(sat)-T2 - ( VBE(on)-T1 + VF-D1 )Here VCE(sat)-T2 is the collector-emitter saturation voltage of the conducting T2, VBE(on)-T1 is the base-emitter on voltage of T1 and VF-D1 is the forward voltage of D1.
Once in state 1 the circuit will charge the capacitors C1 and C2 as specified. The transition to state 2 will occur when the charging of C2 completes and the base-emitter current of T1 increases. This increase will raise the voltage over R1 thus pushing the base voltage of T2 through C1 down. T2 will decrease its conductance and the voltage over R4 will raise. This will increase the base voltage of T1 and the process will result in positive feedback which will switch the circuit to conduncting T1 and non-conducting T2. During state 2 the capacitors charging will take the reverse path.
In each state of the circuit, one of the capacitors is charging through the collector (R1 or R4) and the other capacitor is discharging through the base resistor (R3 or R2). The switching occurs when the capacitor charging throught the base resistor get charged. So this charging process should take longer, i.e. the base resistor should be greater than the collector resistor:
(3.) R2 > R4
(4.) R3 > R1
There is another condition for the resistors and it comes from the current amplification of each transistor, which is also called the dynamic forward current transfer ratio in common emitter circuit - h21e. R2 and R3 should conform to:
(5.) R2 < R1 * 0.5 * h21e-T1(6.) R3 < R4 * 0.5 * h21e-T2
Where 0.5 is a security factor. Finally, D1 and D2 are used to protect the base-emitter junctions of T1 and T2 from reverse voltage higher than the emitter-base maximum voltage of the used transistors. Normally, this voltage is around -5V for silicon NPN transistors. D1 and D2 are used when the power supply is higher than 5V. C3 and C4 are blocking (filtering) capacitors.
The charging effect of the capacitor through the collector resistor delivers non-rectangular output voltage from the schematic (see fig.1).
 fig.1 |
To obtain uniform rectangular output (fig.2) a variation of the schematic is shown below.
The period T of the periodic process can be approximately calculated with the following equation:
(7.) T = 0.7 * R2 * C2 + 0.7 * R3 * C1Here 0.7 * R2 * C2 is the time constant of state 1 of the circuit and 0.7 * R3 * C1 - of state 2 respectively.
The two output voltage levels V1 and V2 are determined as follows:
(8.) V1 = VCC
(9.) V2 = VCE(sat)-T2
Equation (8.) is valid if we assume that the leackage currents ICEO-T2, IL-C2 and IR-D3are neglected. VCE(sat)-T2 is the collector-emitter saturation voltage of T2.
3. Synthesis
The synthesis of the circuit generally starts with the selection of R1 and R4 resistors according to the needs of power load. Then the base resistors are selected using (5.) and (6.), but not to violate (3.) and (4.). After this step, the periods of state 1 and state 2 are chosen. Finally, the capacitance of C1 and C2 is calculated using (7.).
A sample printed circuit board layout (PCB layout) is shown below.